The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Mar. 08, 2018
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventor:

Shibun Tsuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/11573 (2017.01); H01L 27/1157 (2017.01); H01L 21/762 (2006.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 27/11536 (2017.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 21/76232 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/11536 (2013.01); H01L 27/11573 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/7851 (2013.01); H01L 29/7853 (2013.01); H01L 29/7856 (2013.01); H01L 29/792 (2013.01); H01L 29/4916 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device of the present invention includes: an element isolation part which is disposed between fins and whose height is lower than the height of each fin; a memory gate electrode placed over the fins and the element isolation part with a memory gate insulating film having a charge storage part in between; and a control gate electrode disposed in line with the memory gate electrode. The height of the element isolation part below the memory gate electrode is higher than the height of the element isolation part below the control gate electrode. A mismatch between electron injection and hole injection is improved, rewriting operation speed is accelerated, and reliability is enhanced by making the height of the element isolation part below the memory gate electrode higher than the height of the element isolation part below the control gate electrode as mentioned above.


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