The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Aug. 07, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yasuhito Yoshimizu, Yokkaichi, JP;

Takaumi Morita, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11556 (2017.01); H01L 29/66 (2006.01); G11C 16/04 (2006.01); H01L 27/11521 (2017.01); H01L 27/11565 (2017.01); H01L 27/11582 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 16/0441 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01);
Abstract

A memory device includes first and second conductive layers, first and second semiconductor members, first and second charge storage members, first and second insulating members, and first and second insulating layers. The second conductive layer is distant from the first conductive layer. The first semiconductor member is positioned between the first and second conductive layers. The second semiconductor member is positioned between the first semiconductor member and the second conductive layer. The first insulating layer includes a first region positioned between the first semiconductor member and the first charge storage member and a second region positioned between the first semiconductor member and the second semiconductor member. The second insulating layer includes a third region positioned between the second semiconductor member and the second charge storage member and a fourth region positioned between the second region and the second semiconductor member.


Find Patent Forward Citations

Yoshimizu, Yasuhito. (2020). Memory device and method for manufacturing memory device (U.S. Patent No. 10580784). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10580784

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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