The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Oct. 04, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eun Jung Jo, Suwon-Si, KR;

Han Kim, Suwon-Si, KR;

Yoon Seok Seo, Suwon-Si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/18 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73251 (2013.01); H01L 2225/06548 (2013.01);
Abstract

A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.


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