The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Aug. 14, 2018
Applicant:

Taiyo Yuden Co., Ltd., Tokyo, JP;

Inventors:

Motoi Yamauchi, Tokyo, JP;

Yuki Endo, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/66 (2006.01); H03H 9/05 (2006.01); H01L 23/00 (2006.01); H03H 9/08 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 23/66 (2013.01); H01L 24/14 (2013.01); H01L 25/0655 (2013.01); H03H 9/059 (2013.01); H03H 9/0523 (2013.01); H03H 9/0566 (2013.01); H01L 24/13 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/1713 (2013.01); H01L 2224/17106 (2013.01); H01L 2224/17107 (2013.01); H01L 2224/17179 (2013.01); H01L 2924/014 (2013.01); H03H 9/08 (2013.01);
Abstract

An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps.


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