The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jan. 14, 2019
Applicant:

University of Virginia Patent Foundation, Charlottesville, VA (US);

Inventors:

Elaheh Sadredini, Charlottesville, VA (US);

Gholamreza Rahimi, Charlottesville, VA (US);

Kevin Skadron, Charlottesville, VA (US);

Mircea Stan, Charlottesville, VA (US);

Assignee:

University of Virginia Patent Foundation, Charlottesville, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G11C 11/4093 (2006.01); H03K 19/0175 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 11/406 (2013.01); G11C 11/4087 (2013.01); G11C 11/4094 (2013.01); H03K 19/017581 (2013.01); G11C 11/4091 (2013.01);
Abstract

A finite state machine circuit can include a plurality of rows of gain cell embedded Dynamic Random Access Memory (GC-eDRAM) cells that can be configured to store state information representing all N states expressed by a finite state machine circuit. A number of eDRAM switch cells can be electrically coupled to the plurality of rows of the GC-eDRAM cells, where the number of eDRAM switch cells can be arranged in an M×M cross-bar array where M is less than N, and the number of eDRAM switch cells can be configured to provide interconnect for all transitions between the all N states expressed by the finite state machine circuit.


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