The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Nov. 13, 2017
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Sang Ah Hyun, Chungju-si, KR;

Yunyoung Lee, Icheon-si, KR;

Seok Bo Shim, Hwaseong-si, KR;

Sang Ho Lee, Cheongju-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 29/50 (2006.01); G11C 29/18 (2006.01); G11C 29/10 (2006.01); G11C 11/4072 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); G11C 29/18 (2013.01); G11C 29/50016 (2013.01); G11C 11/408 (2013.01); G11C 11/4072 (2013.01); G11C 29/10 (2013.01); G11C 2211/4068 (2013.01);
Abstract

A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.


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