The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Aug. 03, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jin-Ho Kim, Gyeonggi-do, KR;

Sung-Lae Oh, Chungcheongbuk-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 11/419 (2006.01); G11C 11/408 (2006.01); G11C 11/4074 (2006.01); G11C 11/418 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 5/066 (2013.01); G11C 11/4074 (2013.01); G11C 11/4087 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

A semiconductor memory device includes a plurality of pass transistors disposed along a first direction over a substrate, and configured to transfer operating voltages to a memory cell array; and a plurality of global lines formed in a first wire layer over the pass transistors, extending in a second direction intersecting with the first direction, and configured to transfer the operating voltages to the corresponding pass transistors respectively. The global lines are disposed in first direction pitches of some pass transistors among the pass transistors.


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Quick Actions:

Kim, Jin-Ho. (2020). Semiconductor memory device and layout scheme of global lines over pass transistors (U.S. Patent No. 10580461). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10580461

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