The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Aug. 31, 2016
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Xiaobing Lee, Santa Clara, CA (US);

Feng Yang, Portland, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 3/0631 (2013.01); G06F 3/0685 (2013.01); G06F 3/061 (2013.01); G06F 3/0683 (2013.01); G06F 3/0688 (2013.01);
Abstract

A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.


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