The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Dec. 02, 2015
Applicant:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Inventors:

Chanyoung Hwang, Seoul, KR;

Seungjin Yang, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C12N 5/00 (2006.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01); G06F 1/32 (2019.01); G06F 12/0895 (2016.01); G06F 1/3234 (2019.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 1/32 (2013.01); G06F 1/3275 (2013.01); G06F 12/0842 (2013.01); G06F 12/0895 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/20 (2013.01); G06F 2212/455 (2013.01); G06F 2212/604 (2013.01); G06F 2212/62 (2013.01); Y02D 10/13 (2018.01); Y02D 10/14 (2018.01); Y02D 50/20 (2018.01);
Abstract

An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode.


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