The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Mar. 02, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Chihoko Shigeta, Kunitachi Tokyo, JP;

Yoshihisa Kojima, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01); G06F 12/1027 (2016.01); G06F 12/02 (2006.01); G06F 11/08 (2006.01); G11C 29/04 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1048 (2013.01); G06F 3/0614 (2013.01); G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G06F 11/08 (2013.01); G06F 11/1004 (2013.01); G06F 11/1068 (2013.01); G06F 12/0246 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01); G11C 29/04 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A storage device includes a non-volatile memory and a control circuit that reads data in units of cluster, and erase data in units of logical block which includes a plurality of clusters. Data in each cluster includes a first error correction code and each cluster is arranged in at least one error correction group, each including clusters and a second error correction code. The control circuit performs a refresh operation in units of cluster such that refresh target data in a cluster of a first logical block is moved to a cluster of a second logical block. A first error correction group related to the refresh target data includes the cluster of the first logical block before the moving, and the first error correction group related to the refresh target data includes a cluster of the first logical block and a cluster of the second logical block after the moving.


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