The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2020
Filed:
May. 18, 2018
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
Kenichi Kitamura, Kawasaki, JP;
FUJITSU LIMITED, Kawasaki, JP;
Abstract
An arithmetic unit includes a multiplier multiplying first and second inputs to output a multiplication result, an adder adding the third input to the multiplication result to output a multiplication addition result, a normalization shift circuit shifting the multiplication addition result left with a left shift amount, and a left shift amount prediction circuit. The adder includes a carry-save adder adding a first addition value and a first carry value to the third input and a full adder outputting the multiplication addition result. The left shift amount prediction circuit includes a leading zero count circuit generating a leading zero count, a leading one count circuit generating a leading one count, and a correction circuit correcting the leading one count to zero when NOR of respective least significant bits of the M upper order bits of the second addition value and the second carry value of the full adder is true.