The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Feb. 14, 2018
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventors:

I-Hsun Huang, Hsinchu, TW;

Cheng-Yu Chen, New Taipei, TW;

An-Ming Lee, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/24 (2006.01); G06F 1/06 (2006.01); G06F 13/16 (2006.01); G06F 1/12 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 1/24 (2013.01); G06F 1/06 (2013.01); G06F 1/12 (2013.01); G06F 13/1689 (2013.01); G06F 2211/1097 (2013.01); G11C 7/106 (2013.01); G11C 7/222 (2013.01);
Abstract

A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.


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