The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Dec. 03, 2018
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Il Gon Kim, Seoul, KR;

Sun Hwa Lee, Hwaseong-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1343 (2006.01); H01L 27/32 (2006.01); B41J 15/16 (2006.01); G02F 1/1362 (2006.01); B41J 11/48 (2006.01); B41J 15/18 (2006.01); B65H 20/02 (2006.01); G07B 1/00 (2006.01);
U.S. Cl.
CPC ...
B41J 15/16 (2013.01); B41J 11/485 (2013.01); B41J 15/18 (2013.01); B65H 20/02 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); G07B 1/00 (2013.01); H01L 27/124 (2013.01); B65H 2301/4139 (2013.01); B65H 2404/143 (2013.01); B65H 2404/144 (2013.01); B65H 2404/1421 (2013.01); G02F 2001/134372 (2013.01); G02F 2201/40 (2013.01); H01L 27/326 (2013.01); H01L 27/3262 (2013.01);
Abstract

A display device includes a first substrate; a plurality of gate lines arranged in a row direction on the first substrate; a plurality of data lines arranged in a column direction intersecting the row direction; and a plurality of pixels formed in a plurality of pixel areas defined by the gate and data lines, the plurality of pixels comprising at least a first pixel and a second pixel respectively disposed in a first pixel area and a second pixel area that are immediately adjacent to each other. Each of the first and second pixels comprises a thin film transistor electrically connected to the gate and data lines, and a pixel electrode electrically connected to the thin film transistor. The data lines are disposed-apart by different distances from each other in the column direction. Each of the first and second pixel areas comprises a first edge portion adjacent to one of the gate lines and a second edge portion adjacent to another of the gate lines, a length of the first edge portion being greater than a length of the second edge portion. The thin film transistor is disposed at the first edge portion of the first and second pixel areas.


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