The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Oct. 21, 2015
Applicant:

Honeywell International, Inc., Morris Plains, NJ (US);

Inventors:

Amit Kulkarni, Hyderabad, IN;

Sameer D. Manikfan, Hyderabad, IN;

Raja Sekhar Chanapathi, Telangana, IN;

Parimal Kulkarni, Pune, IN;

Assignee:

Honeywell International Inc., Morris Plains, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/08 (2006.01); H04L 12/26 (2006.01); H04L 5/00 (2006.01); H04L 12/861 (2013.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
H04L 67/06 (2013.01); H04L 5/0044 (2013.01); H04L 43/08 (2013.01); H04L 49/90 (2013.01); H04L 41/0233 (2013.01);
Abstract

An apparatus includes a microcontroller () configured to read from a Management Information Base (MIB) register () of an Ethernet switch () to obtain MIB statistic data () regarding a first Ethernet port of the Ethernet switch. The microcontroller is configured to transmit the obtained MIB statistic data to a field programmable gate array (FPGA) (). The FPGA is configured to receive and store the obtained MIB statistic data in a buffer memory (). The FPGA is configured to encapsulate the obtained MIB statistic data in an Ethernet frame (). The FPGA is configured to determine a vacant time slot during which the Ethernet switch is not transmitting data to an external device (). The FPGA is configured to transmit the Ethernet frame to the external device during the vacant time slot.


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