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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10574431 B1

PDFFull Text
Date of Patent:
Feb. 25, 2020

Filed:

Jan. 30, 2019

Physical layer circuitry for multi-wire interface

Applicant:

M31 Technology Corporation, Hsinchu County, TW;

Inventors:

Ching-Hsiang Chang, Taipei, TW;

Yuan-Hsun Chang, Hsinchu County, TW;

Yueh-Chuan Lu, New Taipei, TW;

Huai-Te Wang, Hsinchu County, TW;

Assignee:

M31 Technology Corporation, Hsinchu County, TW;

Attorney:

Winston Hsu

Primary Examiner:

Joseph J Lauture

Int. Cl.
CPC ...
H03M 13/00 (2006.01); H04L 7/00 (2006.01); H03K 19/21 (2006.01); H03K 3/037 (2006.01); H03K 7/08 (2006.01); G04F 10/00 (2006.01); H03F 3/45 (2006.01); G06F 1/06 (2006.01); H03K 5/14 (2014.01); H03K 5/156 (2006.01); G09G 3/20 (2006.01); H04L 25/02 (2006.01); G09G 5/00 (2006.01); H03M 7/00 (2006.01); H04M 1/38 (2006.01); H04B 1/40 (2015.01); H04B 1/58 (2006.01); H04B 3/00 (2006.01); H04B 1/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0016 (2013.01); G04F 10/005 (2013.01); G06F 1/06 (2013.01); G09G 3/20 (2013.01); G09G 5/003 (2013.01); H03F 3/45475 (2013.01); H03K 3/037 (2013.01); H03K 5/14 (2013.01); H03K 5/1565 (2013.01); H03K 7/08 (2013.01); H03K 19/21 (2013.01); H04L 25/0272 (2013.01); H04L 25/0292 (2013.01); H04L 25/0298 (2013.01); G09G 2370/08 (2013.01); H03F 2200/129 (2013.01); H03F 2203/45116 (2013.01); H03F 2203/45594 (2013.01); H03M 7/00 (2013.01); H04B 1/00 (2013.01); H04B 1/40 (2013.01); H04B 1/581 (2013.01); H04B 3/00 (2013.01); H04M 1/38 (2013.01);
Abstract

A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.

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