The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Sep. 21, 2018
Applicant:

Sanken Electric Co., Ltd., Niiza-Shi, Saitama, JP;

Inventors:

Shunsuke Fukunaga, Saitama, JP;

Taro Kondo, Niiza, JP;

Shinji Kudo, Hiki-Gun, JP;

Assignee:

SANKEN ELECTRIC CO., LTD., Niiza-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7806 (2013.01); H01L 29/0696 (2013.01); H01L 29/08 (2013.01); H01L 29/407 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device in embodiments, may include a device region having: two active trenches, each having at least a gate electrode. Two insulated trenches each having an electrode may be formed between the two active trenches separated by a junction. First p-doped layers may be provided between a first active trench and a first insulated trench, and between a second active trenches and a second insulated trench. Second p-doped layers may be provided between a first insulated trench and a second insulated trench with the junction arranged therebetween. The second p-doped layers may be provided on an external surface of the respective first one and second one of the two insulated trenches at a depth and a thickness set to form a current path when the power semiconductor device is in an OFF state.


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