The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Nov. 08, 2018
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventor:

Tsutomu Kiyosawa, Toyama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7805 (2013.01); H01L 29/0696 (2013.01); H01L 29/086 (2013.01); H01L 29/1045 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/42368 (2013.01); H01L 29/66068 (2013.01); H01L 29/7801 (2013.01); H01L 29/7802 (2013.01); H01L 29/7827 (2013.01); H01L 29/7828 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A method of producing a semiconductor device including steps (A) and (B). Step (A) is preparing a semiconductor epitaxial wafer including a plurality of device regions, each including a body region contacting a semiconductor layer. Step (B) is forming a channel layer contacting at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer. The channel layer contains an impurity at a concentration ranging from 1×10cmto 1×10cm, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the step (B), a condition for the epitaxial growth is controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the impurity in the channel layer are negatively correlated to each other.


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