The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Dec. 28, 2018
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Yu-Chieh Chou, New Taipei, TW;

Hsin-Chih Lin, Hsinchu, TW;

Chang-Xiang Hung, Budai Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/43 (2006.01);
U.S. Cl.
CPC ...
H01L 29/778 (2013.01); H01L 29/432 (2013.01); H01L 29/66462 (2013.01);
Abstract

A HEMT includes a buffer layer disposed on the substrate. A barrier layer is disposed on the buffer layer. A channel layer is disposed in the buffer layer adjacent to an interface of the buffer layer and the barrier layer. A band adjustment layer is disposed on the barrier layer, including a first band adjustment layer, a second band adjustment layer, and a third band adjustment layer from top to bottom. A passivation layer is disposed on the barrier layer adjoining the band adjustment layer. A gate electrode is disposed on the band adjustment layer. Source/drain electrodes are disposed on opposite sides of the gate electrode on the barrier layer through the passivation layer. The first band adjustment layer, the second band adjustment layer, and the third band adjustment layer include N-type doped, undoped, and P-type doped III-V or II-VI semiconductors, respectively.


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