The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Feb. 17, 2016
Applicant:

General Electric Company, Schenectady, NY (US);

Inventor:

Thomas Bert Gorczyca, Schenectady, NY (US);

Assignee:

GENERAL ELECTRIC COMPANY, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/04 (2006.01); H01L 21/324 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4933 (2013.01); H01L 21/049 (2013.01); H01L 21/324 (2013.01); H01L 29/1608 (2013.01); H01L 29/401 (2013.01); H01L 29/4916 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01);
Abstract

In an embodiment, a wide bandgap semiconductor power device, includes a wide bandgap semiconductor substrate layer; an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer; a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and a gate electrode disposed directly over the gate dielectric layer. The gate electrode includes an in-situ doped semiconductor layer disposed directly over the gate dielectric layer and a metal-containing layer disposed directly over the in-situ doped semiconductor layer.


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