The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Jan. 31, 2017
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Inventor:

Takeshi Tawara, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/1004 (2013.01); H01L 29/36 (2013.01); H01L 29/66068 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02447 (2013.01); H01L 21/02529 (2013.01); H01L 21/02579 (2013.01);
Abstract

A silicon carbide semiconductor device, including a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor deposition layer of the first conductivity type, deposited on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration that is lower than that of the silicon carbide semiconductor substrate, a base region of a second conductivity type, selectively provided in the first silicon carbide semiconductor deposition layer at a front surface thereof, and a second silicon carbide semiconductor deposition layer of the second conductivity type, deposited on the front surface of the first silicon carbide semiconductor deposition layer. The base region has an impurity concentration of 1×10to 1×10/cmand a thickness of 0.3 to 1.0 μm. The second silicon carbide semiconductor deposition layer has a surface defect density of 3 defects/cm.


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