Semiconductor memory device of three-dimensional structure

Abstract

A semiconductor memory device includes a logic structure including a peripheral circuit element which is formed over a substrate, a bottom dielectric layer which covers the peripheral circuit element and a bottom wiring line which is disposed in the bottom dielectric layer and is coupled to the peripheral circuit element; a memory structure stacked over the logic structure in a first direction perpendicular to a top surface of the substrate; a bit line disposed over a first top dielectric layer which covers the memory structure, extending in a second direction parallel to the top surface of the substrate, and divided into first and second bit line sections; and a power pad disposed over the first top dielectric layer between the first bit line section and the second bit line section, and coupled to the bottom wiring line through a power coupling contact which passes through the memory structure.