The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Sep. 10, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Tatsuyoshi Mihara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/11568 (2017.01); H01L 29/792 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); H01L 27/11 (2006.01); H01L 27/11565 (2017.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); G11C 11/5671 (2013.01); G11C 16/0466 (2013.01); G11C 16/0475 (2013.01); H01L 27/1104 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 21/823468 (2013.01);
Abstract

The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.


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