The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Jul. 23, 2018
Applicant:

Amazing Microelectronic Corp., New Taipei, TW;

Inventors:

Chih-Wei Chen, Taoyuan, TW;

Yu-Shu Shen, Chiayi County, TW;

Kun-Hsien Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/082 (2006.01); H01L 23/60 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); H01L 23/60 (2013.01); H01L 27/082 (2013.01); H01L 21/761 (2013.01); H01L 21/76224 (2013.01);
Abstract

A transient voltage suppression device with improved electrostatic discharge (ESD) robustness includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second doped well having the second conductivity type, a second heavily-doped area having the first conductivity type, and a first current blocking structure. The first doped well is arranged in the semiconductor substrate. The first heavily-doped area is arranged in the first doped well. The second doped well is arranged in the semiconductor substrate. The second heavily-doped area is arranged in the second doped well. The first current blocking structure is arranged in the semiconductor substrate, spaced from the bottom of the semiconductor substrate, and arranged between the first doped well and the second doped well.


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