The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2020
Filed:
Dec. 12, 2017
University of Florida Research Foundation, Incorporated, Gainesville, FL (US);
The University of Connecticut, Farmington, CT (US);
Mark M. Tehranipoor, Gainesville, FL (US);
Domenic J. Forte, Gainesville, FL (US);
Navid Asadizanjani, Gainesville, FL (US);
Qihang Shi, Farmington, CT (US);
University of Florida Research Foundation, Incorporated, Gainesville, FL (US);
The University of Connecticut, Farmington, CT (US);
Abstract
A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.