The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2020
Filed:
Jan. 17, 2019
Applicant:
Denso Corporation, Kariya, Aichi-pref., JP;
Inventor:
Mutsuya Motojima, Kariya, JP;
Assignee:
DENSO CORPORATION, Kariya, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/50 (2006.01); G11C 29/38 (2006.01); G11C 29/14 (2006.01); G06F 11/22 (2006.01); G01R 31/3185 (2006.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01); G11C 7/10 (2006.01); G11C 7/24 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G01R 31/28 (2013.01); G01R 31/3185 (2013.01); G01R 31/31701 (2013.01); G06F 11/22 (2013.01); G11C 7/1096 (2013.01); G11C 7/24 (2013.01); G11C 29/14 (2013.01);
Abstract
A semiconductor apparatus includes a nonvolatile memory therein and an input terminal configured to receive a test control signal and an input signal of a writing/erasing voltage from an external device. The semiconductor apparatus includes: an output terminal; a positive pulse detection circuit configured to detect a positive test control signal, and output the positive test control signal to the output terminal; and a negative pulse detection circuit configured to detect a negative test control signal, and output the negative test control signal to the output terminal after inverting.