The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Dec. 08, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

James S. Fields, Jr., Austin, TX (US);

Andrew D. Walls, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 16/20 (2006.01); G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G11C 16/20 (2013.01); G06F 3/0611 (2013.01); G06F 3/0644 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 12/0802 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G06F 2003/0691 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/222 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism associates the first memory buffer with an address of the write operation. The mechanism performs a compare operation to compare a previous and a next address with respect, to an address associated with the first memory buffer with a plurality of buffers. The mechanism assigns a link tag to at least one buffer identified in the compare operation and the first memory buffer to form a linked buffer set. The mechanism writes to the first memory buffer based on the memory command. The mechanism builds at least one input/output command to persist contents of the linked buffer set and writes the contents of the linked buffer set to at least one solid state drive according to the at least one input/output command.


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