The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Feb. 28, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Masatoshi Ishii, Yokohama, JP;

Nobuyuki Ohba, Sendai, JP;

Atsuya Okazaki, Setagaya-ku, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 11/54 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 11/54 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01);
Abstract

A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.


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