The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2020
Filed:
Feb. 11, 2019
Applicant:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Inventors:
Masanao Yamaoka, Hachioji, JP;
Koichiro Ishibashi, Warabi, JP;
Shigezumi Matsui, Nishitokyo, JP;
Kenichi Osada, Kawasaki, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 11/417 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/146 (2013.01); G11C 5/147 (2013.01); G11C 11/417 (2013.01); G11C 11/4125 (2013.01); G11C 2207/2227 (2013.01);
Abstract
A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.