The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Feb. 08, 2017
Applicant:

Square, Inc, San Francisco, CA (US);

Inventors:

Max Guise, San Francisco, CA (US);

Isreal Blagdan, Oakland, CA (US);

Bradley T Hall, San Francisco, CA (US);

Trent Weber, San Francisco, CA (US);

Assignee:

Square, Inc., San Francisco, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06Q 20/00 (2012.01); H04L 29/06 (2006.01); G06F 21/86 (2013.01); G07G 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 21/86 (2013.01); G07G 1/12 (2013.01);
Abstract

A tamper-proof computing device used in conducting a point-of-sale transaction. The tamper-proof computing device comprises a touch-screen display. In some embodiments, an ITO layer is deposited on the touch-screen display that has a tamper line embedded in the ITO layer, such that the tamper line is susceptible to breaking upon unauthorized physical manipulation, and the tamper line is in communication with a microcontroller that is configured to detect the tamper, and to render the tamper-proof computing device inoperable. The tamper line can be a single line trace embedded in the ITO layer or a cluster of traces embedded in the ITO layer. A method of manufacturing comprises forming a tamper line in an ITO layer, depositing the ITO layer on the display and coupling the tamper line to a security microcontroller.


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