The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2020
Filed:
Jun. 29, 2017
Applicant:
Bar-llan University, Ramat-Gan, IL;
Inventors:
Assignee:
Bar-Ilan University, Ramat-Gan, IL;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 21/55 (2013.01); H04L 9/00 (2006.01); H04L 9/12 (2006.01); H03K 19/00 (2006.01); G06F 21/75 (2013.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 21/556 (2013.01); G06F 21/75 (2013.01); G06F 21/755 (2017.08); H03K 19/0013 (2013.01); H03K 19/00315 (2013.01); H04L 9/003 (2013.01); H04L 9/12 (2013.01); G06F 2217/78 (2013.01); G06F 2221/034 (2013.01);
Abstract
A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.