Hardware control of cpu hold of a cache line in private cache where cache invalidate bit is reset upon expiration of timer

Abstract

A memory access control includes a tracker configured to receive cache invalidate (XI) commands from the memory controller and to provide responses to the memory controller and an address storage element in the tracker that stores an address to be locked by one of the processing units. The system also includes a lock required, a cache invalidate (XI) tracker bit, a set input that upon receipt of a set command sets the lock required bit when a first condition is met, a first reset input that resets the lock required bit upon receipt of a reset command; and a second reset input that resets the XI tracker bit. The tracker rejects incoming XI commands from the memory controller when the lock required bit is set, allows incoming XI commands when the lock bit is not set and sets the XI tracker bit when a first incoming XI command is received.