The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 25, 2020
Filed:
Sep. 26, 2018
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Ehsan Ghasemi, San Jose, CA (US);
Elliott Delaye, San Jose, CA (US);
Ashish Sirasao, San Jose, CA (US);
Sean Settle, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/544 (2006.01); G06N 3/02 (2006.01); G06T 1/60 (2006.01); G06N 3/08 (2006.01);
U.S. Cl.
CPC ...
G06F 7/5443 (2013.01); G06N 3/02 (2013.01); G06N 3/08 (2013.01); G06T 1/60 (2013.01); G06T 2207/20084 (2013.01);
Abstract
A and a request generator circuit is configured to read data elements of a three-dimensional (3-D) input feature map (IFM) from a memory and store a subset of the data elements in one of a plurality of N line buffers. Each line buffer is configured for storage of M data elements. A pixel iterator circuit is coupled to the line buffers and is configured to generate a sequence of addresses for reading the stored data elements from the line buffers based on a sequence of IFM height values and a sequence of IFM width values.