The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Sep. 06, 2015
Applicants:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, CN;

Inventor:

Xing Ming, Shenzhen, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1335 (2006.01); G02F 1/1362 (2006.01); G02F 1/00 (2006.01); G02F 1/1343 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
G02F 1/133516 (2013.01); G02F 1/0063 (2013.01); G02F 1/1343 (2013.01); G02F 1/1362 (2013.01); G02F 1/133621 (2013.01); G02F 2001/133357 (2013.01); G02F 2001/136222 (2013.01); G02F 2001/136231 (2013.01);
Abstract

A method for manufacturing an array substrate and an array substrate are disclosed. The method comprises the steps of forming a plurality of control electrodes on a baseplate, and forming a color-resist region between two adjacent control electrodes, wherein the color-resist region is a first color-resist region, a second color-resist region, a third color-resist region, and a fourth color-resist region in sequence; forming a first color-resist in the first color-resist region, forming a second color-resist in the second color-resist region, and forming a third color-resist in the third color-resist region; and coating the baseplate on which the control electrodes, the first color-resist, the second color-resist, and the third color-resist are formed and the fourth color-resist region with a transparent photoresist so as to form a flat layer. In the method according to the present disclosure, the production efficiency of the array substrate can be improved.


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