The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Feb. 10, 2016
Applicant:

Ushio Denki Kabushiki Kaisha, Tokyo, JP;

Inventors:

Seiji Kitamura, Tokyo, JP;

Masaki Inoue, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
F21V 29/502 (2015.01); B23K 35/26 (2006.01); B23K 35/02 (2006.01); C09K 11/77 (2006.01); H05B 33/14 (2006.01); F21V 9/08 (2018.01); F21V 9/30 (2018.01); F21V 29/89 (2015.01); F21K 9/64 (2016.01); F21S 2/00 (2016.01); C22C 13/00 (2006.01); C22C 9/00 (2006.01); C22C 5/02 (2006.01); C22C 9/01 (2006.01); C22C 9/06 (2006.01);
U.S. Cl.
CPC ...
F21V 29/502 (2015.01); B23K 35/0233 (2013.01); B23K 35/262 (2013.01); C09K 11/7774 (2013.01); F21K 9/64 (2016.08); F21S 2/005 (2013.01); F21V 9/08 (2013.01); F21V 9/30 (2018.02); F21V 29/89 (2015.01); H05B 33/14 (2013.01); B23K 35/26 (2013.01); C22C 5/02 (2013.01); C22C 9/00 (2013.01); C22C 9/01 (2013.01); C22C 9/06 (2013.01); C22C 13/00 (2013.01);
Abstract

The present invention has as its object the provision of a fluorescence light source apparatus which provides a high emission efficiency of a fluorescent plate and a sufficiently high fluorescence intensity. According to the present invention, the fluorescence light source apparatus includes a fluorescent plate that receives excitation light to emit fluorescence, and a heat dissipation substrate that dissipates heat generated in the fluorescent plate, the fluorescent plate and the heat dissipation substrate being bonded via a solder layer, wherein the solder layer has a void ratio of not more than 75% and a maximum void diameter of not more than 0.4 mm. The solder layer may preferably have a void ratio of not more than 50% and a maximum void diameter of not more than 0.2 mm.


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