The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Dec. 06, 2017
Applicant:

Nutanix, Inc., San Jose, CA (US);

Inventors:

Minghui Yang, Fremont, CA (US);

Timothy Sujay Isaacs, San Jose, CA (US);

Ajaykrishna Raghavan, Santa Clara, CA (US);

Dmitri Bronnikov, Foster City, CA (US);

Jaya Singhvi, Cupertino, CA (US);

Peihong Huang, San Jose, CA (US);

Varun Kumar Arora, Santa Clara, CA (US);

Assignee:

Nutanix, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/35 (2006.01); H03M 13/15 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/356 (2013.01); G06F 11/1076 (2013.01); H03M 13/154 (2013.01);
Abstract

Dynamic erasure coding for computing and data storage systems. A method embodiment commences upon accessing a set of fault tolerance policy attributes associated with the computing and data storage system. The topology of the system is analyzed to form mappings between the computing nodes of the system and the availability domains of the system. Based on the fault tolerance policy attributes, the topology, and the generated mapping, a plurality of feasible erasure coding configurations are generated. The feasible erasure coding configurations are scored. One or more high-scoring feasible erasure coding configurations are selected and deployed to the computing and data storage system. The method is repeated when there is a change in the fault tolerance policy attributes or in the topology. Depending on the topology and/or the nature of a change in the topology, more than one erasure coding configurations can be deployed onto the computing and data storage system.


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