The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

May. 10, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David Paulsen, Inver Grove Heights, MN (US);

Phil Paone, Rochester, MN (US);

John E. Sheets, II, Zumbrota, MN (US);

George Paulik, Rochester, MN (US);

Karl Erickson, Rochester, MN (US);

Gregory J. Uhlmann, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/34 (2006.01); H03M 1/16 (2006.01); H03M 1/12 (2006.01); H03M 1/36 (2006.01);
U.S. Cl.
CPC ...
H03M 1/16 (2013.01); H03M 1/1245 (2013.01); H03M 1/361 (2013.01);
Abstract

A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number 'n.' The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an ninput of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2*a unit capacitance (C). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.


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