The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Sep. 14, 2015
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shinji Nishizono, Tokyo, JP;

Tadashi Shimizu, Tokyo, JP;

Tomohiro Nishiyama, Tokyo, JP;

Norikazu Motohashi, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02K 11/33 (2016.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H02M 7/537 (2006.01); H02P 27/06 (2006.01);
U.S. Cl.
CPC ...
H02K 11/33 (2016.01); H01L 23/528 (2013.01); H01L 24/48 (2013.01); H02M 7/537 (2013.01); H01L 2224/48105 (2013.01); H02P 27/06 (2013.01);
Abstract

A first semiconductor device having a power transistor for switching is mounted on a power wiring substrate PBa semiconductor device PKGhaving a driving circuit for driving the first semiconductor device and a semiconductor device PKGhaving a control circuit for controlling the semiconductor device PKGare mounted on a first principal surface of a control wiring substrate PBand a semiconductor device PKGhaving a regulator circuit is mounted on a second principal surface of the control wiring substrate PBOn the first principal surface of the control wiring substrate PBthe semiconductor device PKGand the semiconductor device PKGare mounted in a second area out of the second area and a third area adjacent to each other via a first area in which a plurality of holes HCare arranged. On the second principal surface of the control wiring substrate PBthe semiconductor device PKGis mounted in a fifth area out of a fourth area positioned opposite the second area and the fifth area positioned opposite the third area.


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