The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Jan. 25, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung-gil Yang, Hwaseong-si, KR;

Sang-su Kim, Yongin-si, KR;

Sun-wook Kim, Seongnam-si, KR;

Geum-jong Bae, Suwon-si, KR;

Seung-min Song, Hwaseong-si, KR;

Soo-jin Jeong, Bucheon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02603 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42356 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/7855 (2013.01);
Abstract

A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.


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