The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Jul. 27, 2018
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Samuele Sciarrillo, Usmate Velate, IT;

Paolo Colpani, Agrate Brianza, IT;

Ivan Venegoni, Bareggio, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/76852 (2013.01); H01L 23/3171 (2013.01); H01L 23/5283 (2013.01); H01L 24/02 (2013.01); H01L 23/525 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/14 (2013.01);
Abstract

A semiconductor device includes a passivation layer, an interconnection metallizationhaving a peripheral portion over the passivation layer, and an outer surface coatingon the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.


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