The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2020
Filed:
Apr. 08, 2018
Fanuc Corporation, Yamanashi, JP;
Hitoshi Izumi, Yamanashi, JP;
Kenichiro Kurihara, Yamanashi, JP;
FANUC CORPORATION, Yamanashi, JP;
Abstract
A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.