The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2020

Filed:

Oct. 04, 2018
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Justin L. Ha, Hayward, CA (US);

Frederick K. H. Lee, Mountain View, CA (US);

Seungjune Jeon, Santa Clara, CA (US);

Assignee:

DELL PRODUCTS L.P., Round Rock, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0617 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/34 (2013.01);
Abstract

A system for controlling a solid state drive is disclosed that includes a plurality of NAND memory devices, each NAND memory device further comprising at least one die, a plurality of blocks associated with each of the dies, and a plurality of pages associated with each of the blocks. A pseudo clock system configured to determine a pseudo clock value for each of the NAND memory devices. An effective retention time system coupled to the plurality of NAND memory devices and configured to determine a maximum effective retention time for each of the NAND memory devices as a function of the pseudo clock value for the NAND memory device.


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