The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Aug. 25, 2017
Applicant:

Tactotek Oy, Oulunsalo, FI;

Inventors:

Tero Heikkinen, Oulunsalo, FI;

Antti Keranen, Oulunsalo, FI;

Mikko Heikkinen, Oulunsalo, FI;

Jarmo Saaski, Oulunsalo, FI;

Assignee:

TACTOTEK OY, Oulunsalo, FI;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); F21V 3/00 (2015.01); F21V 8/00 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H05K 3/28 (2006.01); H05K 3/46 (2006.01); F21Y 115/10 (2016.01); F21Y 115/15 (2016.01);
U.S. Cl.
CPC ...
H05K 1/0313 (2013.01); F21V 3/00 (2013.01); G02B 6/0011 (2013.01); H05K 1/0269 (2013.01); H05K 1/0274 (2013.01); H05K 1/038 (2013.01); H05K 1/181 (2013.01); H05K 3/28 (2013.01); H05K 3/284 (2013.01); H05K 3/4644 (2013.01); F21Y 2115/10 (2016.08); F21Y 2115/15 (2016.08); H05K 1/0393 (2013.01); H05K 3/4632 (2013.01); H05K 2201/0108 (2013.01); H05K 2201/0129 (2013.01); H05K 2201/10106 (2013.01); H05K 2203/1316 (2013.01); H05K 2203/1327 (2013.01);
Abstract

Integrated multilayer structure () for hosting electronics, comprising a first substrate () comprising organic, electrically substantially insulating natural material including and exhibiting a related naturally grown or natural textile based surface texture, said first substrate having a first side (A) facing a predefined front side of the structure, said first side of the first substrate being optionally configured to face a user and/or use environment of the structure or of its host device, and an opposite second side (B), a plastic layer (), optionally comprising thermoplastic or thermoset plastics, molded onto said second side of the first substrate so as to at least partially cover it, and circuitry (B) provided on the second side of the first substrate, said circuitry being at least partially embedded in the molded material of the plastic layer. Related method of manufacture is presented.


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