The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2020
Filed:
Dec. 26, 2017
Applicant:
Seagate Technology Llc, Cupertino, CA (US);
Inventors:
Nitin Kumar Chhabra, Maharashtra, IN;
Rohit Halba, Madhya Pradesh, IN;
Shashi Kumar Shaw, West Bengal, IN;
Shrikrishna Nana Mehetre, Maharashtra, IN;
Assignee:
SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 11/00 (2006.01); H03M 7/30 (2006.01); H04L 25/02 (2006.01); G06F 13/42 (2006.01); H04L 27/06 (2006.01); H03M 5/16 (2006.01); H03K 19/0185 (2006.01); H04L 25/49 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H03M 7/3055 (2013.01); G06F 13/426 (2013.01); H03M 5/16 (2013.01); H04L 25/0276 (2013.01); H04L 27/06 (2013.01); H03K 19/017509 (2013.01); H03K 19/018521 (2013.01); H04L 25/49 (2013.01);
Abstract
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits Nthat can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits N.
Chhabra, Nitin. (2020). Probability-based optimization of system on chip (soc) power (U.S. Patent No. 10560116). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10560116
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile