The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 2020
Filed:
Jun. 15, 2018
Cosmin Iorga, Westlake Village, CA (US);
Cosmin Iorga, Westlake Village, CA (US);
Other;
Abstract
Measurement of power distribution network (PDN) Z-parameters and S-parameters of a programmable logic device (PLD), such as field programmable gate array (FPGA) or complex programmable logic device (CPLD), is performed by configuring and using only logic blocks and I/O blocks commonly available in any existing programmable logic device, without the need of built-in dedicated circuits. The measured models include the PDN elements on the PLD die, PLD package, and PCB. The S-parameter and Z-parameter models can be then used in circuit simulation tools to evaluate the power supply noise in the PLD logic core and the timing jitter in the PLD I/O data links.