The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Apr. 04, 2017
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Atsushi Kamei, Maebashi, JP;

Yasuaki Hayashi, Oura-gun, JP;

Katsumi Yamamoto, Kokubunji, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 7/18 (2006.01); H01M 10/42 (2006.01); H02H 3/00 (2006.01); H01M 10/48 (2006.01); H01M 10/44 (2006.01); H02J 7/00 (2006.01);
U.S. Cl.
CPC ...
H02H 7/18 (2013.01); H01M 10/425 (2013.01); H02H 3/006 (2013.01); H01M 10/44 (2013.01); H01M 10/48 (2013.01); H01M 2010/4271 (2013.01); H01M 2010/4278 (2013.01); H02J 7/0031 (2013.01);
Abstract

A calibration circuit may comprise a negative pack terminal, an intermediate node, and a first protection IC coupled to a first transistor. The first transistor may be coupled between the negative pack terminal and the intermediate node. The calibration circuit may comprise a second protection IC coupled in parallel with the first protection IC and further coupled to a second transistor. A power source may be coupled in parallel with the first and second protection ICs, and a current source may be coupled between the negative pack terminal and the intermediate node, wherein the intermediate node is positioned between the first transistor and the second transistor, and the power source is configured to provide a current to the first protection IC through a first current loop.


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