The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

May. 22, 2019
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Takeshi Kamino, Kawasaki, JP;

Takahiro Tomimatsu, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/28 (2006.01); H04N 5/374 (2011.01); H01L 29/66 (2006.01); H01L 21/266 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14689 (2013.01); H01L 21/266 (2013.01); H01L 21/28123 (2013.01); H01L 21/28518 (2013.01); H01L 27/1461 (2013.01); H01L 27/1462 (2013.01); H01L 27/14612 (2013.01); H01L 27/14685 (2013.01); H01L 29/665 (2013.01); H04N 5/374 (2013.01);
Abstract

An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.


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