The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Apr. 01, 2019
Applicant:

Sakai Display Products Corporation, Sakai-shi, Osaka, JP;

Inventors:

Yuta Sugawara, Sakai, JP;

Takeshi Uno, Sakai, JP;

Nobutake Nodera, Sakai, JP;

Takao Matsumoto, Sakai, JP;

Assignee:

SAKAI DISPLAY PRODUCTS CORPORATION, Sakai-shi, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/45 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1229 (2013.01); G02F 1/1368 (2013.01); H01L 27/1285 (2013.01); H01L 29/458 (2013.01); H01L 29/66765 (2013.01); H01L 29/78606 (2013.01); H01L 29/78678 (2013.01); H01L 29/78696 (2013.01); G02F 2202/103 (2013.01); G02F 2202/104 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01);
Abstract

A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is higher in crystallinity than the first region and the second region.


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