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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10559586 B1

PDFFull Text
Date of Patent:
Feb. 11, 2020

Filed:

Mar. 01, 2018

Semiconductor memory device

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Taichi Iwasaki, Yokkaichi Mie, JP;

Takeshi Sonehara, Yokkaichi Mie, JP;

Hiroyuki Nitta, Kuwana Mie, JP;

Assignee:

Toshiba Memory Corporation, Tokyo, JP;

Attorney:

Kim & Stewart LLP

Primary Examiner:

Marc Anthony Armand

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 27/11556 (2017.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 23/00 (2006.01); H01L 27/11565 (2017.01); H01L 23/58 (2006.01); H01L 21/78 (2006.01); H01L 27/11519 (2017.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/3212 (2013.01); H01L 21/32053 (2013.01); H01L 21/32055 (2013.01); H01L 21/7684 (2013.01); H01L 21/76816 (2013.01); H01L 21/76846 (2013.01); H01L 21/78 (2013.01); H01L 27/11519 (2013.01); H01L 29/1037 (2013.01); H01L 29/7883 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01);
Abstract

A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.

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