The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Feb. 07, 2017
Applicants:

Eun Yeoung Choi, Hwaseong-si, KR;

Bio Kim, Seoul, KR;

Young Wan Kim, Hwaseong-si, KR;

Jung Ho Kim, Seongnam-si, KR;

Young Seon Son, Hwaseong-si, KR;

Jae Young Ahn, Seongnam-si, KR;

Byong Hyun Jang, Suwon-si, KR;

Inventors:

Eun Yeoung Choi, Hwaseong-si, KR;

Bio Kim, Seoul, KR;

Young Wan Kim, Hwaseong-si, KR;

Jung Ho Kim, Seongnam-si, KR;

Young Seon Son, Hwaseong-si, KR;

Jae Young Ahn, Seongnam-si, KR;

Byong Hyun Jang, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42368 (2013.01);
Abstract

A semiconductor device including a dielectric layer is provided. The semiconductor device includes a stack structure, and a vertical structure within the stack structure. The vertical structure includes a lower region having a first width and an upper region having a second width, greater than the first width. The vertical structure further includes two dielectric layers of which respective ratios of lower thicknesses in the lower region to upper thicknesses in the upper region are different from each other.


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