The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2020

Filed:

Mar. 07, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Dong-kil Yun, Hwaseong-si, KR;

Chan-ho Kim, Seoul, KR;

Pan-suk Kwak, Seoul, KR;

Hong-soo Jeon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11526 (2017.01); H01L 27/11529 (2017.01); H01L 29/94 (2006.01); H01L 27/11556 (2017.01); H01L 27/112 (2006.01); H01L 27/108 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11529 (2013.01); H01L 27/10897 (2013.01); H01L 27/11286 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 29/94 (2013.01); G11C 11/5621 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01);
Abstract

A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.


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